This invention relates, in general, to methods of forming circuit packages, and more particularly, to a method for forming a semiconductor power circuit package.
Semiconductor devices are encapsulated within packages for protection from damage by external stresses and to provide a means for carrying electrical signals to and from the devices. Included in the repertoire of semiconductor device package types are dual-in-line packages, pin grid array packages, TAB packages, and multichip modules. More particularly, power semiconductor device packages may be formed as modules having a high thermal conductivity which are capable of dissipating large amounts of heat.
One type of power semiconductor device module includes a copper baseplate to which an isolation pad is mounted. The isolation pad may include a ceramic layer sandwiched between two thin copper sheets. One of the thin copper sheets is bonded to the copper baseplate wherein the copper baseplate serves as a heat sink. Semiconductor die are mounted to the second thin copper sheet and a leadframe is attached to the semiconductor die. Subsequently, the semiconductor die and a portion of the leadframe are encapsulated by a molding compound.
Although methods for manufacturing modules for power semiconductor devices have been taught in the prior art, these modules are not optimized for heat dissipation. In particular, the isolation pad and the copper baseplate have significantly different coefficients of thermal expansion. Thus, under conditions of high heat dissipation the copper baseplate may expand at a faster rate than the isolation pad thereby warping the isolation pad and potentially decreasing the reliability of the module. In addition, delamination of the thin copper sheets from the ceramic layer may result from mismatches between the coefficients of thermal expansion of the thin copper sheets and the ceramic layer.
Further, long power leads are typically soldered to the semiconductor device die. The die are not only stressed by the step of soldering the leads to the die but they are mechanically stressed by external forces which may be applied to the leads. In addition, the use of the long power leads inherently introduces both a parasitic inductance and a parasitic resistance, particularly at high operating frequencies. Other disadvantages include a requirement for a large number of piece parts and extra processing steps to form the parts into a package thereby increasing the cost of the package.
Accordingly, it would be advantageous to have a semiconductor device package that is a unitary package comprising components having similar coefficients of thermal expansion. Additionally, it is desirable that the inherent parasitic components such as parasitic inductances and resistances be minimized in the unitary package. Moreover, decreasing the number of piece parts in packages would lower the manufacturing cost as well as the cost for components. Finally, it would be advantageous to have a packaging method in which fragile semiconductor die, such as gallium arsenide die, may be reliably and inexpensively packaged.